LOT: Logic Optimization with Testability. New transformations for logic synthesis
نویسندگان
چکیده
منابع مشابه
LOT: Logic Optimization with Testability. New transformations for logic synthesis
A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel c...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 1998
ISSN: 0278-0070
DOI: 10.1109/43.703921